Now Apply the HIGH logic at the “J” then you may notice that Q is turned one, but when you even tried to change the logic at “J”, it will not be affected. Now here we will understand the other two states. The clock pulse is continuously changing with time to change the output.
This whole process will follow the truth table as we mentioned above. When we give the logic one state on the J and zero on K then we receive the one on the Q and zero on Q’, and when we send the zero on J and one on K then we receive the one Q’ and zero on Q. In Proteus first, understand how Flip Flop will work. JK Flip Flop used as Memory and Control Registers.Due to its fast speed, it was widely used to control the specific LED Pattern.The latching and EEPROM circuit uses the JK Flip Flop.X = No change of Pulse APPLICATION of 74LS73 DUAL JK FLIP-FLOP TRUTH TABLE FOR JK FLIP FLOP CLOCK PULSE INPUTS OUTPUTS DETAIL CLK J K Q Q’ X 0 0 1 0 NO CHANGE X 0 0 0 1 L – H 0 1 1 0 Same as SR Latch X 0 1 0 1 L – H 1 0 0 1 X 1 0 1 0 L – H 1 1 0 1 Toggle Action L – H 1 1 1 0 The following outputs will be done on given inputs. This clocking process between Master and Slave makes the flip flop to transfer the data from the master to slave with a timing signal. The output of Master Latch will be given to the Slave when there will be HIGH to LOW pulse to the Input gate of Slave Latch. The output will be ignored in case of LOW Pulse. When the clock is LOW then there will be no output. To give the output to the master when the CLOCK get a rising pulse. The output of the NAND gates has been attached to anther pin which is known as clock pin. The input signal of Master is connected to the NAND Gates. The output of the Slave latch to Master helps the JK flip flop to toggle. The two NAND gates and Slave SR latch gives the input to Master SR Latch. The first latch is used as Master and another SR latch is used as Slave. JK flip flop comes up with two SR latch and four NAND gates as you can see in the below image. The clock controls the change in output with the input state. So, to solve this issue in JK flip-flop an internal clock has been installed.
There are four logic states in which SR latch operates, which is when there is different input on both input pins but when there are same outputs then in case of 1,1 the output becomes invalid and in case of 1,1 the output becomes unpredictable. The output should be HIGH at least one pin and another pin should be at a LOW state. First, one is Reset and the Second one is known as a set. To understand 74LS73 we need to understand SR latch first. 74LS73 comes with two types of packing, SOIC, and PDIP.Its operating temperature range is 0 – 70 degree and the charge storage temperature range is -65 to 150 degrees.It doesn’t have any error state and invalid state like some other latches.74LS73 could store two bits at the same time.It could store a single bit like other latches but it has the ability to give the toggle and no change state.It operates for all kind of TTL/EMOS devices.INPUT J-1 Pin 14 Pin 14 used as a second input for first JK flip flop. OUTPUT 1Q (bar) Pin 13 Pin 13 gives the inverted output from the first JK flip flop. OUTPUT 1Q Pin 12 Pin 12 gives the non-inverted output from first JK flip flop. GROUND Pin 11 The ground pin is used to apply the ground of power supply and to make the common ground of another circuit with IC. INPUT K-2 Pin 10 Pin 10 is used as an input pin for second JK flip flop. OUTPUT 2Q Pin 9 Pin 9 is used as the non-inverted output of the second JK flip flop. OUTPUT 2Q (bar) Pin 8 Pin 8 is used as an inverted output of second JK flip flop. INPUT J-2 Pin 7 It is used to send the second input of JK flip flop. LOW pulse will be used to reset the data from the flip flop. 2CLR (bar) Pin 6 Pin 6 is used as a reset pin by second JK flip-flop. Change of pulse from LOW to HIGH used to change the state. 2CLK Pin 5 Pin 5 is used to provide the clock to the second JK flip flop in 74LS73. VCC Pin 4 Vcc is used to apply the power supply to the JK flip flop to the whole IC.
INPUT K-1 Pin 3 K-1 is the input pin used to send the bit to the JK flip flop. LOW pulse will be used to clear the data from the flip flop. 1CLR (BAR) Pin 2 Pin 2 used as resent pin for first flip-flop. Change of pulse is used to change the state. PIN CONFIGURATION of 74LS73 PINS DESCRIPTION 1 CLK Pin 1 Pin 1 is the clock pin for first JK flip-flop.